Package-on-package assembly and method for manufacturing the same

ABSTRACT

A package-on-package assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one TSV chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the TSV chip comprises at least one TSV connecter and is mounted on the first side through a plurality of second bumps arranged within the peripheral area; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and a plurality of solder bumps mounted on the second side.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductorpackaging, and more particularly to a Package-on-Package (PoP) assemblyand a method for manufacturing the same.

2. Description of the Prior Art

With recent advancements in the semiconductor manufacturing technologymicroelectronic components are becoming smaller and circuitry withinsuch components is becoming increasingly dense. To reduce the dimensionsof such components, the structures by which these components arepackages and assembled with circuit boards must become more compact. Inorder to meet the requirements of smaller footprints with higherdensities, 3D stacking packaging such as PoP (Package-on-Package)assembly has been developed.

A PoP assembly typically includes a top package with a device die bondedto a bottom package with another device die. In PoP designs, the toppackage may be interconnected to the bottom package through peripheralsolder balls. However, the prior art PoP assembly is not able to providevery tight pitch stacking. Further, the prior art PoP assembly has largepackage form factor and poor warpage control.

In wafer level packaging, the wafer and the dies mounted on the waferare typically covered with a relatively thick layer of the moldingcompound. The thick layer of the molding compound results in increasedwarping of the packaging due to coefficient of thermal expansion (CTE)mismatch, and the thickness of the packaging. It is known that waferwarpage continues to be a concern. Warpage can prevent successfulassembly of a die-to-wafer stack because of the inability to maintainthe coupling of the die and wafer. Warpage issue is serious especiallyin a large sized wafer, and has raised an obstacle to a wafer levelsemiconductor packaging process that requires fine-pitch RDL process.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a semiconductor devicehaving package-on-package (PoP) configuration.

In one aspect of the invention, a package-on-package (PoP) assemblyincludes a bottom die package and a top die package mounted on thebottom die package. The bottom die package includes an interposer havinga first side and a second side opposite to the first side; at least oneactive chip mounted on the first side within a chip mounting areathrough a plurality of first bumps; at least one through-substrate-via(TSV) chip mounted on the first side within a peripheral area beingadjacent to the chip mounting area, wherein the TSV chip comprises atleast one TSV connecter and is mounted on the first side through aplurality of second bumps arranged within the peripheral area; a moldingcompound disposed on the first side, the molding compound covering theat least one active chip and the at least one TSV chip; and a pluralityof solder bumps mounted on the second side.

According to one embodiment of the invention, the top die package ismounted on the bottom die package through a plurality of third bumpsdisposed on the TSV chip.

In one aspect of the invention, a package-on-package (PoP) assemblyincludes a bottom die package and a top die package mounted on thebottom die package. The bottom die package includes an interposer havinga first side and a second side opposite to the first side; at least oneactive chip mounted on the first side within a chip mounting areathrough a plurality of first bumps; at least one dummy chip mounted onthe first side within a peripheral area being adjacent to the chipmounting area, wherein the dummy chip is directly mounted on apassivation layer of the interposer; a dielectric layer covering the atleast one active chip and the at least one dummy chip; at least one TSVconnecter penetrating through the dielectric layer and the dummy chip; amolding compound disposed on the first side, the molding compoundcovering the at least one active chip and the at least one TSV chip; anda plurality of solder bumps mounted on the second side.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the embodiments, and are incorporated in and constituteapart of this specification. The drawings illustrate some of theembodiments and, together with the description, serve to explain theirprinciples. In the drawings:

FIG. 1 to FIG. 9 are schematic, cross-sectional diagrams showing anexemplary method for fabricating a package-on-package (PoP) assemblyaccording to one embodiment of the invention; and

FIG. 10 to FIG. 20 are schematic, cross-sectional diagrams showing anexemplary method for fabricating a package-on-package (PoP) assemblyaccording to another embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings, which form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments maybe utilized and structural changes maybe made without departing from the scope of the present invention.

The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

One or more implementations of the present invention will now bedescribed with reference to the attached drawings, wherein likereference numerals are used to refer to like elements throughout, andwherein the illustrated structures are not necessarily drawn to scale.The terms “die”, “semiconductor chip”, and “semiconductor die” are usedinterchangeable throughout the specification.

The terms wafer and substrate used herein include any structure havingan exposed surface onto which a layer is deposited according to thepresent invention, for example, to form the circuit structure such as aredistribution layer (RDL). The term substrate is understood to includesemiconductor wafers, but not limited thereto. The term substrate isalso used to refer to semiconductor structures during processing, andmay include other layers that have been fabricated thereupon.

Please refer to FIG. 1 to FIG. 9. FIG. 1 to FIG. 9 are schematic,cross-sectional diagrams showing an exemplary method for fabricating apackage-on-package (PoP) assembly according to one embodiment of theinvention.

As shown in FIG. 1, a carrier 300 is prepared. The carrier 300 may be areleasable substrate material with an adhesive layer (not explicitlyshown), but not limited thereto. At least a dielectric layer or apassivation layer 310 is then formed on a top surface of the carrier300. The passivation layer 310 may comprise organic materials such aspolyimide (PI) or inorganic materials such as silicon nitride, siliconoxide or the like.

As shown in FIG. 2, subsequently, a redistribution layer (RDL) 410 isformed on the passivation layer 310. The RDL 410 may comprise at leastone dielectric layer 412 and at least one metal layer 414. Thedielectric layer 412 may comprise organic materials such as polyimide(PI) or inorganic materials such as silicon nitride, silicon oxide orthe like, but not limited thereto. The metal layer 414 may comprisealuminum, copper, tungsten, titanium, titanium nitride, or the like.

According to the illustrated embodiment, the metal layer 414 maycomprise a plurality of first bump pads 415 a and second bump pads 415 bexposed from a top surface of the dielectric layer 412. The first bumppads 415 a are disposed within a chip mounting area 102, while the dummypads 415 b are disposed outside the chip mounting area such as aperipheral area 104 around the chip mounting area 102.

Subsequently, a passivation layer 413 such as polyimide or solder maskmaterial may be formed on the dielectric layer 412. The passivationlayer 413 may include openings (not explicitly shown) that expose therespective first and second bump pads 415 a and 415 b. A conventionalelectroplating solder bumping process may be performed to form firstbumps 416 a and second bumps 416 b on the respective first and secondbump pads 415 a and 415 b.

As shown in FIG. 3, subsequently, individual flip-chips or dies 420 awith their active sides facing down toward the RDL 410 are then mountedon the RDL 410 through the first bumps 416 a to thereby forming astacked chip-to-wafer (C2W) construction. These individual flip-chips ordies 420 a are active integrated circuit chips with certain functions,for example, GPU (graphic processing unit), CPU (central processingunit), memory chips, etc.

According to the illustrated embodiment, a plurality of TSV chips 420 bare mounted in the peripheral area 104 around the chip mounting area 102through the second bumps 416 b. Each of the TSV chips 420 b may comprisea substrate 440 such as a silicon substrate. A plurality of throughsubstrate via (TSV) connecters 441 fabricated within the substrate 440.A plurality of bumps 442 may be formed on a top surface of the substrate440 opposite to the second bumps 416 b.

Optionally, an underfill (not shown) maybe applied under each chip 420a/420 b. Thereafter, a thermal process may be performed to reflow thefirst bumps 416 a and second bumps 416 b.

After the chip-bonding process, a molding compound 500 is applied. Themolding compound 500 covers the attached active chips 420 a and the TSVchips 420 b and the top surface of the RDL 410. The molding compound 500may be subjected to a curing process. The mold compound 500 may comprisea mixture of epoxy and silica fillers, but not limited thereto.

As shown in FIG. 4, a top portion of the molding compound 500 may bepolished away to expose top surfaces of the active chips 420 a and aportion of the bumps 442 of the TSV chips 420 b. During the moldingcompound grinding process, a portion of the chips 420 a maybe removed,but not limited thereto. At this point, the top surfaces of the activechips 420 a are flush with the top surface of the molding compound 500.

As shown in FIG. 5, a bump forming process is performed to form bumps444 directly and respectively on the exposed bumps 442 of the TSV chips420 b. These bumps 444 protrude from the top surface of the moldingcompound 500 for further connections. According to the illustratedembodiment, the bumps 444 may be formed by using electroplating methods,but not limited thereto. The bumps 444 may comprise copper, nickel, tin,or any suitable solderable material known in the art.

As shown in FIG. 6, the wafer level package is then adhered to anothercarrier 600. The bumps 444 face toward, and may contact, the carrier600. The carrier 600 may be a glass substrate, but not limited thereto.Optionally, an adhesive layer or a glue layer 602 may be used.Subsequently, the carrier 300 is removed to thereby expose a majorsurface of the passivation layer 310. The RDL 410 and the passivationlayer 310 function as an interposer. The de-bonding of the carrier 300may be performed by using a laser process or UV irradiation process, butnot limited thereto.

As shown in FIG. 7, after de-bonding the carrier 300, openings may beformed in the passivation layer 310 to expose respective solder pads,and then solder bumps or solder balls 520 may be formed on therespective solder pads. Thereafter, the carrier 600 and the adhesivelayer 602 are removed to expose the bumps 444.

As shown in FIG. 8, after the carrier 600 and the adhesive layer 602 areremoved, the wafer level package is then diced and singulated intoindividual die package 10. For example, the wafer level package may befirst attached to a dicing tape (not shown), where the bumps 520 facetoward, and may contact, the dicing tape.

As shown in FIG. 9, a die package 20 comprising at least a moldedsemiconductor die 201 is mounted on the die package 10 to thereby form aPoP assembly 1. The die package 20 may be electrically connected to thedie package 10 through the bumps 444 and the TSV chips 420 b.

It is advantageous to use the invention because most of the peripheralarea 104 around the chip mounting area 102 is occupied by the TSV chips420 b, the used amount of the molding compound 500 is reduced, andtherefore the warpage of the wafer or die package is alleviated oravoided.

Please refer to FIG. 10 to FIG. 20. FIG. 10 to FIG. 20 are schematic,cross-sectional diagrams showing an exemplary method for fabricating apackage-on-package (PoP) assembly according to another embodiment of theinvention, wherein like numeral numbers designate like layers, regions,or elements.

As shown in FIG. 10, likewise, a carrier 300 is prepared. The carrier300 may be a releasable substrate material with an adhesive layer (notexplicitly shown), but not limited thereto. At least a dielectric layeror a passivation layer 310 is then formed on a top surface of thecarrier 300. The passivation layer 310 may comprise organic materialssuch as polyimide (PI) or inorganic materials such as silicon nitride,silicon oxide or the like.

As shown in FIG. 11, subsequently, a redistribution layer (RDL) 410 isformed on the passivation layer 310. The RDL 410 may comprise at leastone dielectric layer 412 and at least one metal layer 414. Thedielectric layer 412 may comprise organic materials such as polyimide(PI) or inorganic materials such as silicon nitride, silicon oxide orthe like, but not limited thereto. The metal layer 414 may comprisealuminum, copper, tungsten, titanium, titanium nitride, or the like.

According to the illustrated embodiment, the metal layer 414 maycomprise a plurality of bump pads 415 a exposed from a top surface ofthe dielectric layer 412. The bump pads 415 a are disposed within a chipmounting area 102. The metal layer 414 may comprise a plurality of pads415 b disposed within a peripheral area 104 around the chip mountingarea 102.

Subsequently, a passivation layer 413 such as polyimide or solder maskmaterial may be formed on the dielectric layer 412. The passivationlayer 413 may include openings (not explicitly shown) that expose therespective bump pads 415 a. A conventional electroplating solder bumpingprocess maybe performed to form bumps 416 a on the respective bump pads415 a.

As shown in FIG. 12, subsequently, individual flip-chips or dies 420 awith their active sides facing down toward the RDL 410 are then mountedon the RDL 410 through the first bumps 416 a to thereby forming astacked chip-to-wafer (C2W) construction. These individual flip-chips ordies 420 a are active integrated circuit chips with certain functions,for example, GPU (graphic processing unit), CPU (central processingunit), memory chips, etc.

According to the illustrated embodiment, a plurality of dummy chips (orwarpage-control chips) 420 c are mounted in the peripheral area 104around the chip mounting area 102. According to the illustratedembodiment, the dummy chips 420 c may comprise silicon or dummy siliconchip. According to the illustrated embodiment, the dummy chips 420 c maybe attached onto the passivation layer 413 by using an adhesive (notshown).

Optionally, an underfill (not shown) maybe applied under each chip 420a. Thereafter, a thermal process may be performed to reflow the firstbumps 416 a and second bumps 416 b.

After the chip-bonding process, a molding compound 500 is applied. Themolding compound 500 covers the attached active chips 420 a and thedummy chips 420 c and the top surface of the RDL 410. The moldingcompound 500 may be subjected to a curing process. The mold compound 500may comprise a mixture of epoxy and silica fillers, but not limitedthereto.

As shown in FIG. 13, likewise, a top portion of the molding compound 500may be polished away to expose top surfaces of the active chips 420 aand top surfaces of the dummy chips 420 c . During the molding compoundgrinding process, a portion of the chips 420 a may be removed, but notlimited thereto. At this point, the top surfaces of the active chips 420a and the top surfaces of the dummy chips 420 c are flush with the topsurface of the molding compound 500.

As shown in FIG. 14, a dielectric layer 610 such as a silicon oxidelayer is deposited onto the top surfaces of the active chips 420 a, thetop surfaces of the dummy chips 420 c, and the top surface of themolding compound 500. According to the illustrated embodiment, thedielectric layer 610 is deposited in blanket fashion. Thereafter, anetching process is performed to form through substrate vias (TSVs) 620into the dielectric layer 610 and the dummy chips 420 c. The TSVs 620expose respective pads 415 b in the peripheral area 104.

As shown in FIG. 15, an isolation oxide layer 630 is formed on thesidewalls of the TSVs 620. For example, a conformal silicon oxide layeris deposited on the sidewalls and bottom surfaces of the TSVs 620 and onthe dielectric layer 610. A dry etching process may be performed to etchaway the silicon oxide layer from the bottom surfaces of the TSVs 620 toexpose the pads 415 b.

As shown in FIG. 16, a metal filling process is then performed. Each ofthe TSVs 620 is filled with a metal layer 650. According to theillustrated embodiment, the TSVs 620 may not be completely filled withthe metal layer 650. A lithographic process and an etching process maybe performed to form a metal trace pattern 652 such as a bump pad on thedielectric layer 610.

As shown in FIG. 17, the wafer level package is then adhered to anothercarrier 600. The metal trace pattern 652 faces toward, and may contact,the carrier 600. The carrier 600 may be a glass substrate, but notlimited thereto. Optionally, an adhesive layer or a glue layer (notshown) may be used to attach the wafer level package to the carrier 600.Subsequently, the carrier 300 is removed to thereby expose a majorsurface of the passivation layer 310. The de-bonding of the carrier 300may be performed by using a laser process or UV irradiation process, butnot limited thereto.

As shown in FIG. 18, after de-bonding the carrier 300, openings may beformed in the passivation layer 310 to expose respective solder pads,and then solder bumps or solder balls 520 may be formed on therespective solder pads. Thereafter, the carrier 600 and the adhesivelayer 602 are removed to expose the metal trace pattern 652.

As shown in FIG. 19, after the carrier 600 and the adhesive layer 602are removed, the wafer level package is then diced and singulated intoindividual die package 10. For example, the wafer level package may befirst attached to a dicing tape 700, where the solder bumps 520 facetoward, and may contact, the dicing tape 700.

As shown in FIG. 20, a die package 20 comprising at least a moldedsemiconductor die 201 is mounted on the die package 10 to thereby form aPoP assembly 1 a. The die package 20 may be electrically connected tothe die package 10 through the bumps 252, the metal trace pattern 652and the TSVs 620.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A package-on-package (PoP) assembly, comprising: a bottom die packagecomprising a TSV-less interposer having a first side and a second sideopposite to the first side; at least one active chip mounted on thefirst side within a chip mounting area through a plurality of firstbumps; at least one through-substrate-via (TSV) chip mounted on thefirst side within a peripheral area being adjacent to the chip mountingarea, wherein the TSV chip comprises at least one TSV connecter and ismounted on the first side through a plurality of second bumps arrangedwithin the peripheral area; a molding compound disposed on the firstside, the molding compound covering the at least one active chip and theat least one TSV chip, wherein a top surface of the at least one activechip is flush with a top surface of the molding compound; and aplurality of solder bumps mounted on the second side; a top die packagemounted on the bottom die package, wherein the top die package iselectrically connected to the bottom die package only through the TSVchip within the peripheral area.
 2. The PoP assembly according to claim1, wherein the TSV-less interposer comprises a redistribution layer(RDL).
 3. The PoP assembly according to claim 2, wherein the RDLcomprises at least one dielectric layer and at least one metal layer. 4.The PoP assembly according to claim 1, wherein the top die packagecomprises at least a molded semiconductor die.
 5. The PoP assemblyaccording to claim 1, wherein the top die package is mounted on thebottom die package through a plurality of third bumps disposed on theTSV chip. 6-9. (canceled)